1. Field of the Invention
The present invention relates to a semiconductor device, more particularly to a field memory that is used for memorizing picture data (one screen) for displaying on a display screen.
2. Description of Related Art
FIG. 2 is a block diagram showing an example of the conventional field memory.
This field memory includes a Y decoder 30S, a shift redundancy circuit 20S, and a sub-register block 10S for storing the picture data for the first row of the display screen, a memory cell block 40 for storing picture data after the second row, and so forth.
The sub-register block 10S includes m+1 registers including an auxiliary to the number m (m is an integer) of pictures for one row of the display screen. The Y decoder 30S selects one of the m column lines by decoding a column address signal ADY and outputs a column signal when an enabling signal SEN for a sub-register block is provided at the time of displaying the first row. The input side of a shift redundancy circuit 20S is connected to the m column lines. Here, the enabling signal SEN is a signal for indicating the picture element position of the picture data, and indicates the first row of the picture data as the top portion.
The shift redundancy circuit 20S corresponds between the m column lines and the m+1 registers of the sub-register block 10S. The shift redundancy circuit 20S includes a fuse group for changing connection and a switch group for changing a connection condition based on the condition of this fuse group. For the shift redundancy circuit 20S, in the condition where all the fuses are not cut off, each of the first to m-th input sides is connected to each of the first to m-th output sides. Further, when an i-th (i is a positive integer below m) fuse is cut off, each of the first to ixe2x88x921-th input sides is connected to each of the first to ixe2x88x921-th output sides in a direct manner, and each of the i-th to m-th input sides is connected to each of the i+1 to m+1-th output sides by shifting one respectively. Accordingly, when the i-th register of the sub-register block 10S is broken, the broken fuse can be disregarded by cutting off the i-th fuse of the shift redundancy circuit 20S.
On the other hand, the memory cell block 40 memorizes the picture data of the second to n-th (n is a positive integer greater than 2) row. The memory cell block 40 is composed of nxe2x88x921 word lines arranged in a parallel way, m+1 bit lines arranged in a crossing way thereto, and respective memory cells arranged in respective crossing points between such respective word lines and such bit lines. The word line of the memory cell block 40 is connected to an X decoder 50 that decodes a row address signal ADX and drives the corresponding word line. For the memory cell block 40, when one word line is driven by the X decoder 50, each of the m+1 memory cells corresponding thereto is selected and connected to each corresponding bit line.
The resister block 10R is connected to the m+1 bit lines of the memory cell block 40 using a sense amplifier block 60. A sense amplifier block 60 amplifies a tiny potential difference, which is output to respective bit lines from the memory cell of the memory cell block 40 at the time of a read-out operation, until the predetermined logical level is attained. The resister block 10R temporarily memorizes data, which is read and/or written to the memory cell of the memory cell block 40, one line at a time. In the same way as the sub-register block 10S, the column signal is provided to the resister block 10R based on the column address signal ADY from a Y decoder 30R using a shift redundancy circuit 20R.
A read write (R/W) buffer 70S that performs write-in or read-out to a register, which is selected sequentially by the column signal, is connected to the sub-register block 10S. In the same way, a read write buffer 70R that performs write-in or read-out to a register, which is selected sequentially by the column signal, is connected to the register block 10R. The read write buffers 70S and 70R are connected to selectors 80 and 90. As a result, write-in data DTW is provided from the outside through the selector 80, and read-out data DTR is output to the outside through the selector 90.
In such a field memory, it is tested whether or not write-in or read-out is performed to the sub-register block 10S register at the stage of manufacturing and it is checked whether or not a failure condition has occurred. If the failure register is found in the checked registers, the fuse corresponding thereto of the shift redundancy circuit 20S is cut off and then the failure register thereof is eliminated. Further, it is tested whether or not write-in or read-out is performed to the memory cell of the memory cell block 40 and it is checked whether or not the failure has occurred. If the failure memory cell is found in the memory cell block, the fuse corresponding thereto of the shift redundancy circuit 20R is cut off and the failure memory cell thereof is then eliminated.
In this field memory, the data write-in is performed in the following way. When m data of the first column of the display screen is written in, the selector 80 is switched towards the read write buffer 70S. Further, the enabling signal SEN for the sub-register block is provided to the Y decoder 30S, the column address signal ADY is decoded by this Y decoder 30S, and then the column signal is provided to the sub-register block 10S by way of the shift redundancy circuit 20S.
On the other hand, the write-in data DTW is provided to the sub-register block 10S by way of the selector 80. Accordingly, the write-in data DTW provided to the column address signal ADY in a synchronizing manner is written sequentially in respective registers of the sub-register block 10S.
When the data after the second row of the display screen is written in, the selector 80 is switched towards the read write buffer 70R. Further, the enabling signal REN for the register block is provided to the Y decoder 30R, the column address signal ADY is decoded by this Y decoder 30R, and then the column signal is provided to the resister block 10R using the shift redundancy circuit 20R. The enabling signal REN is a signal for indicating the picture element position of the picture data and indicates the picture data other than the top position, namely after the second row.
On the other hand, the write-in data DTW is provided to the resister block 10R through the selector 80. Accordingly, the write-in data DTW that is provided by synchronizing with the column address signal ADY is written sequentially in respective registers of the resister block 10R. When the write-in data DTW for one row is stored in respective registers of the resister block 10R, the contents of respective registers of this resister block 10R are output to the memory cell block 40 by way of the sense amplifier block 60 and the bit lines. Accordingly, the write-in data DTW for one row is written simultaneously in the memory cell connected to the word line selected by the X decoder 50.
Further, in this field memory, the data read-out is performed in the following way. When m data of the display screen is read out, the selector 90 is switched towards the read write buffer 70S. Further, the enabling signal SEN is provided to the Y decoder 30S, the column address signal ADY is decoded by this Y decoder 30S, and then the column signal is provided to the 30 sub-register block 10S using the shift redundancy circuit 20S.
Accordingly, the contents of respective registers of the sub-register block 10S are readout sequentially by synchronizing with the column address signal ADY, and then the read-out data DTR is output from the selector 90.
When the data after the second row of the display screen is read out, the selector 90 is switched towards the read write buffer 70R. Further, the contents of the memory cell for one row connected to the word line selected by the X decoder 50 are output simultaneously to the resister block 10R using the bit line and the sense amplifier block 60. Furthermore, the enabling signal REN is provided to the Y decoder 30R, the column address signal ADY is decoded by this Y decoder 30R, and then the column signal is provided to the resister block 10R using the shift redundancy circuit 20R. Accordingly, the data for one row read out in the resister block 10R from the memory cell block 40 are read out sequentially in the read write buffer 70R by synchronizing with the column address signal ADY, and output from the selector 90 as the read-out data DTR.
However, according to the conventional field memory, two sets of the Y decoders 30S and 30R and shift redundancy circuits 20S and 20R have been required to corresponding the sub-register block 10S and the resister block 10R, and thus there has been a problem, in which the scale of the circuit has become large.
The present invention solves the problem which the above-mentioned technology has, and provides the field memory in which the scale of the circuit is simplified.
Here, all of the necessary characteristics which the present invention requires are not disclosed in the summary of the invention, but sub-combinations of these characteristics can also be the present invention.
In order to attain the above-mentioned object, a semiconductor device includes a first register for enabling a predetermined part of the picture data composed of a plurality of bits to be stored corresponding to a first selection signal; a memory array cell, which includes a plurality of memory cells being arranged in a matrix way in row and column directions, for storing a residual part of the picture data; a second register for enabling data that is stored in the memory cell array to be output or for enabling data being output from the memory cell array to be stored corresponding to a second selection signal; and a control circuit for selectively generating and outputting the first selection signal or the second selection signal based on position information of the picture data.
The above-mentioned object can be attained by composing in this way.
Further, the semiconductor device of the present invention includes a first register for enabling a predetermined part of the picture data composed of a plurality of bits to be stored corresponding to decoding information and a first selection signal for indicating position information of the picture data; a memory array cell, which includes a plurality of memory cells being arranged in a matrix way in row and column directions, for storing a residual part of the picture data; a second register for enabling data being stored in the memory cell array to be output or data being output from the memory cell array to be stored corresponding to the decoding information and a second selection signal for indicating another position information of the picture data; and a decode circuit for generating and outputting decoding information by decoding address information.
The above-mentioned object can also be attained by composing in this way.
Another semiconductor device of the present invention includes a first register for enabling a predetermined part of the picture data composed of a plurality of bits to be stored corresponding to decoding information and a first selection signal for indicating position information of the picture data; a memory array cell, which includes a plurality of memory cells being arranged in a matrix way in row and column directions, for storing a residual part of the picture data; a second register for enabling data being stored in the memory cell array to be output or data being output from the memory cell array to be stored corresponding to the decoding information and a second selection signal for indicating another position information of the picture data; and a control circuit for selectively generating the first selection signal or the second selection signal based on position information of the picture data and for outputting generated selection signals corresponding to a clock signal synchronizing with the picture data.
The above-mentioned object can also be attained by composing in this way.